1. Field of the Invention
The present invention relates, in general, to a semiconductor memory device, and, in particular, to a semiconductor memory device provided with an internal circuit to be initialized upon start of supply of a supply voltage. The invention has a particular applicability to a dynamic random access memory device.
2. Description of the Background Art
In recent years, semiconductor memories such as dynamic random access memories (which will be called as "DRAMs"), static random access memories (which will be called as "SRAMs") and serial access memories have been integrated more highly, and various function circuits have been added thereto. Generally, the semiconductor memories have been used in various electronic equipments such as a computer.
Generally, a supply voltage starts to be supplied to a semiconductor memory when the supply voltage starts to be supplied to an electronic equipment. The semiconductor memory is internally provided with various function circuits, as described above. These function circuits must be initialized or reset before the start of normal operation of the semiconductor memory.
An internal circuit using a counter circuit can be exemplified as the function circuit to be initialized or reset upon start of the supply of supply voltage. For example, the DRAM has a self-refresh function for automatically or periodically refreshing a data signal stored in a memory cell array, as is well known. For carrying out the self-refresh operation, the DRAM includes a counter for generating a refresh address, i.e., refresh counter. Since output data of the refresh counter can be arbitrary immediately after the supply of supply voltage, the state of the refresh counter must be initialized or reset before the start of the normal refresh operation.
Similarly, a serial access memory such as a video RAM having a serial access function includes a serial counter for sequentially selecting serial data to be sent therefrom. Also the serial counter must be initialized or reset before the start of the normal serial access operation.
In the conventional semiconductor memory, the function circuit or internal circuit described above is initialized or reset by carrying out an initializing mode or reset mode called a "dummy cycle" immediately after the supply of supply voltage. For this purpose, conventionally, a state control signal such as a row address strobe signal /RAS is externally applied, and the dummy cycle is carried out under this external state control signal.
When the dummy cycle is carried out, a clock signal generator disposed in the DRAM initializes various internal function circuits (e.g., refresh counter) in response to toggle of the signal /RAS. Since the normal operation cannot start without initializing the internal function circuit, as described above, it is essential to apply the toggle of the signal /RAS to the DRAM from an externally disposed circuit immediately after the supply of the supply voltage.
The invention can be applied to various semiconductor memories such as DRAM, SRAM and serial access memory, but description will be made on an example in which the invention is applied to the DRAM.
FIG. 4 is a block diagram of a conventional DRAM. Referring to FIG. 4, a DRAM 200 includes a memory cell array 58 including a large number of memory cells disposed in rows and columns, a row decoder 55 for selecting a row in the memory cell array 58 to be accessed, a column decoder 56 for selecting a column to be accessed, a sense amplifier 63 for amplifying data signals read from selected cells, and an I/O gate circuit 57 for selecting a bit line pair in response to an output signal supplied from the column decoder 56. An address buffer 54 receives externally applied address signals A0-A9. The address signals A0-A9 include row address signals RA0-RA8 and column address signals CA0-CA8 in a time sharing manner. The row address signals RA0-RA8 are applied to the row decoder 55. The column address signals CA0-CA8 are applied to the column decoder 56. The address signal A9 is applied to an I/O controller 65.
A clock signal generator 51 receives an external state control signal for controlling the operation state of the DRAM 200, and specifically it receives a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, an output enable signal /OE and the like. The clock signal generator 51 applies clock signals for controlling the timing to various circuits disposed in the DRAM 200 in response to these state control signals.
The DRAM 200 has the self-refresh function described before. For carrying out the self-refresh, the DRAM 200 further includes a refresh counter 53 for generating a refresh address, and a refresh controller 52 for controlling the refresh counter 53. The refresh controller 52 is responsive to a refresh control signal Srf applied from the clock signal generator 51 to apply a counter control signal Scc for controlling the refresh counter 53 to the refresh counter 53. The refresh counter 53 is responsive to the counter control signal Scc to apply refresh addresses Q0-Q8 to the address buffer 54. The address buffer 54 is responsive to the refresh addresses Q0-Q8 applied thereto to apply the row address signals RA0-RA8 for therefresh to the row decoder 55. The row decoder 55 sequentially selects the memory cell rows in the memory cell array 58, whereby the data signals stored in the memory cell array 58 are refreshed.
In the write operation, input data Di to be stored in the memory cell array 58 is applied to an input buffer 59, and then is applied through an I/O line 66 and the I/O gate circuit 57 to the bit line pair (not shown) selected by the column decoder 56. The data signal applied to the bit line pair is stored in the memory cells (not shown) selected by the row decoder 55.
In the read operation, the data signals stored in the memory cells selected by the row decoder 55 are amplified by a sense amplifier 63. The signal selected from the amplified data signals by the column decoder 56 is applied through the I/O gate circuit 57 and the I/O line 66 to an output buffer 60. The output buffer 60 amplifies the data signal applied thereto, and then externally supplies the amplified signal as output data Do.
Also in the DRAM 200 shown in FIG. 4, it is necessary to carry out the foregoing dummy cycle immediately after the start of supply of a supply voltage Vcc. Specifically, after the start of supply of the supply voltage Vcc, an externally disposed circuit (not shown) applies signals /RAS, which are repeated for several cycles, e.g., eight cycles, to the clock signal generator 51. In other words, it is necessary for carrying out the dummy cycle to apply signals /RAS, which are repeated, e.g., for eight cycles, from the externally disposed circuit. The clock signal generator 51 is responsive to the toggle of signal /RAS to apply a refresh control signal Srf for initializing or resetting the refresh counter 53 to the refresh controller 52. The refresh controller 52 is responsive to the signal Srf to apply a counter control signal Scc for initializing or resetting the refresh counter to the refresh counter 53. Therefore, the refresh counter 53 is reset prior to the normal self-refresh operation.
The clock signal generator 51 initializes or resets not only the refresh counter 53 but also various internal function circuits (not shown) disposed in the DRAM 200 immediately after the start of supply of the supply voltage Vcc. In order to carry out the initializing or resetting operation by the clock signal generator 51, the toggle of signal /RAS must be applied from the externally disposed circuit. This means that the external circuit is required to generate the toggle of a special signal /RAS for the initialization, resulting in an increase of a load on the external circuit, e.g., system side in a computer system.